(1) Field of the Invention
The present invention relates to a method for manufacturing semiconductors, in particular to a method for neutralizing the undesirable side-effects that result from a post oxide rapid thermal anneal.
(2) Description of the Prior Art
As the internal dimensions of integrated circuits grow ever smaller (less than 1 micron line width for example), the possibility of small amounts of misalignment between successively created features grows larger. Thus, for example, the contact hole etched in a passivating layer of BPSG (borophosphosilicate glass) may not align perfectly with the previously created S/D (source and drain) contact in a MOSFET (metal-oxide-semiconductor field effect transistor) device. Such misalignment can then lead to shorting of the S/D contact to the substrate. This problem is particularly severe for NMOS devices in memory where tighter design rules require a smaller cell size.
One way of overcoming shorting of the S/D contact to the substrate (that occurred as a result of misalignment) is to implant a layer of appropriate donor or acceptor atoms, using standard ion implantation methods, just below the surface of the S/D via hole. In this way, the original S/D contact is, in effect, spread out so that it covers the entire floor of the S/D via hole. Now, a metallic layer, deposited into the S/D via hole, will make contact only with the source or drain and not the underlying substrate.
As part of the standard ion implantation methods referred to above, it is necessary to activate the implanted ions. This is normally achieved by means of a suitable heat treatment, typically 30 minutes at about 850.degree. C. Unfortunately this relatively long heating time is sufficient to allow some phosphorus to diffuse out of the passivating BPSG layer into the PMOS sections of a CMOS (complementary MOS)-type integrated circuit which leads to high contact resistance at the P+ S/D contact.
As an alternative to this approach, with its attendant problems, the implanted ions can be activated by using a rapid thermal anneal (RTA) cycle, typically 800.degree. to 1100.degree. C. for about 10 to 30 seconds. This is adequate for the activation of the ion implanted material without being long enough for significant phosphorus diffusion to occur.
While the RTA method is generally preferred for the activation of the N-type dopants, for the above mentioned reasons, it is subject to undesired side-effects of its own. In particular, RTA can lead to the creation of interface states in the gate oxides of the MOS devices. These interface states have a disastrous effect on the lifetime of minority carriers in a semiconductor as taught, for example, by Pankove et al (U.S. Pat. No. 4,113,514 Sep. 12, 1978). This means that, for a given applied voltage, the thickness of the depletion region underneath the gate oxide will be reduced. This, in turn, reduces the source-drain transconductance, reducing the gain of the MOS device.
This major undesirable side-effect of the RTA process (namely the creation of interface states in the gate oxides of MOS devices) can be largely eliminated by following the RTA cycle with an additional heat treatment. Devices are heated for 30 minutes at 450.degree. C., which is substantially lower than the 800.degree.-1100.degree. C. range quoted earlier for the RTA, in hydrogen or in a mixture of hydrogen and an inert gas such as nitrogen.
Previously used methods for the treatment of semiconductors by heating in hydrogen have required the in situ creation of a low pressure hydrogen discharge (gas plasma). See for example Pankove et al. (U.S. Pat. No. 4,113,514 Sep. 12, 1978) or Chenevas-Paule et al. (U.S. Pat. No. 4,331,486 May 25, 1982). The method of the current invention requires neither low pressure operation nor the creation of a gaseous plasma.